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    Main problems and solutions of pipeline

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    [Abstract]:
    Main problems and solutions of pipeline
    In the process of running water, the following three kinds of related conflicts often occur, causing the flow line to be cut off.
    1. Resource related
    Resource c
    Main problems and solutions of pipeline
    In the process of running water, the following three kinds of related conflicts often occur, causing the flow line to be cut off.
    1. Resource related
    Resource correlation refers to the conflict that occurs when multiple instructions enter the assembly line and compete for the same function part within the same machine clock cycle. Suppose an instruction pipeline consists of five segments. As can be seen from the table below, at clock 4, I1 and I4 instructions have a conflict over memory resources.
    Resource related conflicts occur when two instructions access memory at the same time
    Solutions to resource-related conflicts:
    First, the I4 instruction stops for one beat before starting. The other is to add a memory, placing instructions and data in two separate memory.
    2. Data correlation
    In a program, if you have to wait until the previous instruction is executed before you can execute the latter, then the two instructions are data-dependent.
    In a flow computer, the processing of instructions is overlapped. Before the previous instruction is finished, the second and third instructions start to work successively. Due to the overlapping processing of multiple instructions, data correlation conflicts occur when the number of operations required by subsequent instructions is just the result of the operation of the previous instruction. As shown in the table below, the ADD instruction has a data-related conflict with the SUB instruction.
    Two instructions have data-related conflicts
    Solutions to data-related conflicts:
    A number of operation result buffer registers are set up in the running CPU's arithmetic unit to keep the operation result temporarily so that the subsequent instruction can be used directly, which is called "forward" or directional transmission technology.
    3. Control correlation
    Control related conflicts are caused by transfer instructions. When the transfer instruction is executed, the next instruction may be taken for the order according to the result of the transfer condition. It is also possible to move to a new target address to fetch instructions, thus causing the pipeline to break.
    In order to reduce the effect of transfer instruction on pipeline performance, the following two transfer processing techniques are commonly used:
    Delay transfer method: the compiler rearranges the instruction sequence to achieve. The basic idea is to "execute first and then transfer", which means that when a transfer takes place, the instruction pipeline is not empty, but a few instructions that have entered the assembly line immediately after the transfer instruction Ib. If these instructions are useful instructions that are not relevant to the Ib results, the delay loss time slice is being used effectively.
    Transfer prediction method: the hardware method is used to predict the future behavior according to the past behavior of the instruction. By prefetching the queue and the target instruction cache by using the transfer fetch and sequential fetch instructions, the transfer prediction can be carried forward to the finger fetch stage to obtain good results.
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